The present invention relates to time-to-charge conversion with low jitter and phase offset in a phase/frequency locking loop, as might be used in an integrated circuit requiring clock recovery. More specifically, one embodiment of the present invention provides a "time-to-charge" converter circuit which addresses the problem of conversion of a delta time width between two input signal pulses into a delta current while minimizing the noise generated and producing a zero delta current when an input delta time width is zero.
One application of a time-to-charge converter is a charge pump of a phase-locked loop ("PLL"), where a delta time between a reference clock edge and an oscillator clock edge is converted to a delta current (charge) to be sinked into or sourced from a capacitor in a loop filter at the input of a voltage controlled oscillator ("VCO") which outputs the oscillator clock.
Frequency synthesis using phase information and PLL's is known in the art. See, for example, Egan, W., Frequency Synthesis by Phase, pp. 115-123 (1981) and Gardner, F. M., "Charge-Pump Phase-Lock Loops", IEEE Trans. on Comm., Vol. COM-28, No. 11, pp. 1849-1858 (1980), which are incorporated by reference herein for all purposes.
A PLL typically comprises a phase/frequency detector with a reference clock input and an oscillator clock input (the clocks being locked). The outputs of the detector are up/down pulse signals. A pulse signal from the detector has a width which is a function of the timing between the two clock inputs. One of the pulse signals has a width that is related to a lag period between an edge of the reference clock and an edge of the oscillator clock, while the other pulse signal has a width that is related to a lead period between an edge of the reference clock and an edge of the oscillator clock. Where there is neither lag nor lead, the pulses are at their minimum. The minimum pulse width can be zero, but is more often a function of a delay through a signal path in the detector. The pulse widths for the up and down signals are also equal, unless there is an offset in the charge pump which requires an offset in the input to have a zero delta current at the output.
These two pulse signals connect to a charge pump which sinks current during a pulse of one of the signals and sources current during a pulse of the other signal. The particular implementation determines which of the up/down outputs correspond to lagging/leading and current sourcing/sinking. In any case, the sourcing and sinking of current affects a voltage across a capacitor (which may be part of a low-pass loop filter), where that voltage in turn is an input to a VCO which outputs the oscillator clock.
Where the PLL is to be implemented in an integrated circuit ("IC"), the problem of where to put the capacitor arises. The capacitor can either be on-chip or off-chip. If the capacitor is on-chip, it might take up large amounts of valuable chip area. Furthermore, large on-chip capacitors tend to pick up signals from unrelated circuits found elsewhere on the chip. If the capacitor is placed off-chip, additional leads must be provided from the IC package to accommodate connection to the external capacitor. Another disadvantage of an off-chip capacitor is the additional labor required to install it relative to the on-chip capacitor.
Unless chip space is freely available or the minimum size (capacitance) of the capacitor is small, the capacitor would have to be off-chip. However, a loop filter capacitor cannot be arbitrarily small, as it must be large enough to absorb the delta current (.DELTA.I, or charge q) sourced or sinked by the charge pump. The delta current cannot be arbitrarily small, as it must be somewhat larger than the noise impinging on the capacitor (noise due to leakage current and noise from the charge pump itself).
Previous charge pumps injected noise into the delta current from several sources. One source is the inputs to the charge pump. In a CMOS circuit where the inputs switch from 3.3 volts to 0.0 volts, the switching will often cause high-frequency transients at the output due to circuit coupling. Another source of noise is the output stage transistors. As the output stage transistors in a charge pump are switched on and off, they must charge and discharge to create and destroy the channel between the drain and source of the transistor. This charge must go somewhere, some of which ends up at the charge pump outputs. If the channel charge from each of the output stage transistors is equal, the dumping of charge onto both charge pump outputs might have little effect on the VCO, as it would cause at most a common mode shift in the capacitor voltage. However, due to process and other variations, it is difficult to make transistors with all the same channel charge characteristics. Where a mismatch occurs in the amount of channel charge stored and storable in the output stage transistors, the charging and discharging of those transistors results in a spurious signal.
Aside from the problem of noise, previous IC-based charge pumps also suffered from mismatches among components. IC's are subject to variations due to process, temperature and voltage variations and these variations will often lead to an imbalance which results in a circuit requiring a nonzero delta time width at the input to reach a zero delta current at the output. This delta time width difference could be adjusted for elsewhere in the PLL, but is not a well controlled quantity, as it varies across varied process, temperature and voltage conditions.
Therefore, what is needed is a PLL with a charge pump which can be implemented as part of an IC to convert a delta time to a delta current where the PLL operates with a low delta current requirement, where the charge pump does not generate large amounts of noise when either of the two input pulse signals has a rising or falling edge and where the charge pump does not require a nonzero delta time width for a zero delta current, or vice versa.